The Tundra Tsi107™ host bridge for PowerPC® provides system interconnect between PowerPC processors, PCI peripherals,  and local memory. The Processor Interface supports Freescale and IBM PowerPC processors at frequencies up to 133 MHz. The device also supports a wide variety of system configurations by providing support for a second processor and a local slave device.

The PCI bus allows system designers to design systems quickly due to the vast number of PCI peripheral devices that are available. The Tsi107 PCI Interface supports frequencies up to 66 MHz, and can operate as both a master and a target on the bus.

The Tsi107 provides many of the other requirements for embedded applications, including a Memory Controller, dual-processor support, two-channel flexible DMA Controller, Interrupt Controller, I²C Controller, and low-skew clock drivers.

Business Benefits

Clock Generation Cost Savings

The integrated Clock Generator of the Tsi107 removes the need for external clock generation and buffering circuitry. Generation of these clocks can add significant costs to the overall system. These include not only the costs of the clock generators and buffers, but also the circuitry associated with these devices such as crystals and filtering components. Along with component costs come the routing constraints imposed by these additional devices.

PCB Cost Savings

The Tsi107 can reduce the space requirements necessary to implement a design, and as a result, save on PCB costs. There are several areas in which the Tsi107 saves board space:

• The integrated Clock Generator removes the need for external clock generators and buffers. This reduces not only the space required for these external devices, but also the cost and power associated with these devices.
• The Tsi107 is offered in a 33 x 33 mm package.
• The Tsi107 supports a 32-bit memory data path. If the 32-bit data path provides sufficient bandwidth for this application, it can result in significant space savings since only half the number of memory devices are required compared to a 64-bit implementation.

In addition, with a 1.27 mm ball pitch and only 503 pins, the routing requirements of the Tsi107 are minimal. This can result in a reduction in the number of PCB layers, further reducing cost.

Memory Cost Savings

The Tsi107 provides a flexible Memory Interface with support for a 64-bit or 32-bit data path. This can result in significant cost, power, and space savings since the memory system can be implemented with only half the number of memory devices; that is, assuming a 32-bit data path can provide sufficient bandwidth for this application.

Performance

With a processor to memory latency of only 8 clock cycles, the Tsi107 offers one of the lowest memory latency of any PowerPC host bridge available today. Processor performance is often limited by memory latency, so the low latency of the Tsi107 can translate into increased performance. Because of the low latency, the Tsi107 is often used as the PowerPC companion chip during benchmarking of new processors from Freescale Semiconductor.