08-029 Staff Engineer, Physical Design (Chip Integration) – Ottawa, ON Tundra Semiconductor Corporation, based in Ottawa, Ontario Canada is the global leader in System Interconnect providing world-class customer support, leading-edge semiconductor solutions and design services to the world’s foremost communications, networking, storage system and information technology vendors. At Tundra, we recognize that hiring the best and brightest talent is a big part of what makes us a successful company. We understand that our greatest asset is our employees. Ever dream of designing the future? Design yourself in. Join the Tundra Team! Position Summary As a Staff Engineer in the Physical Design group you will bring a strong background and demonstrated leadership in chip integration, pad ring planning, sensitive IP placement and analysis, power delivery, ESD/Latch-up integrity and other aspects of physical design for devices in smaller geometries. The proven ability to define and drive these aspects of IC design and work with a team to deliver first pass success silicon is a must. Previous experience with Synopsys Pilot flow, Cadence tools (including layout) and/or experience in layout is considered a plus. Responsibilities In this role you will be responsible for: Pad ring design, analysis and integration Selection and placement of PLLs, I/Os and other sensitive IP High speed circuit integrity methodologies Extraction and SPICE analysis on critical circuits System level timing budgets and board/package requirements for signal integrity Hierarchical physical layout to include clock tree design and distribution Device power delivery and management methodologies Die, package, and PCB power delivery requirements Physical verification (LVS/DRC) IR drop analysis Library prep Tool evaluation and set up
Other possible responsibilities: Hierarchical timing closure to include fixing setup and hold violations Hierarchical floor planning Verilog netlist generation Participate in the selection of Cell library for new 65nm designs and smaller geometries Participate in the development of die size and cost estimation methodologies Define high speed circuit integrity and clocking methodologies Perform quality assurance procedures on hard macros Interface with ESD, Latch up, I/O and layout specialists to ensure silicon integrity Generate block level and top level chip constraints from a functional spec Perform Static Timing Analysis at the chip level Mixed signal IP design Requirements Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent Minimum 6-10 years experience in ASIC development Strong understanding and ability to take a leadership role in aspects of IC Physical Design related to chip integration, pad ring planning, sensitive IP placement and analysis, power delivery, ESD/Latch-up integrity Working knowledge of various physical design tools and platforms, with preference towards Synopsys flow Astro, JupiterXT, PrimeRail, Hercules, StartRCXT and custom layout tools such as Laker and/or Virtuoso Experience with Synopsys DC/PC/ICC (synthesis), Primetime (STA), Formality Good documentation and presentation skills Positive, can-do attitude and the ability to work well in a team environment Knowledge of Verilog or VHDL, Perl, TCL, Unix, MS Windows and MS Office environment and tools Digital design experience using Verilog HDL The ability to collaborate with technical and non-technical peers across multiple sites and an interest in playing a variety of roles within the team. This may require some travel.
If you envision yourself in this role and would like to be part of a team in a dynamic environment, please contact us at 08-029@tundra.com or visit our website at www.tundra.com for more information on our company, products and services. |
