08-027 Manager, Physical Implementation–Ottawa, ON Tundra Semiconductor Corporation, based in Ottawa, Ontario Canada is the global leader in System Interconnect providing world-class customer support, leading-edge semiconductor solutions and design services to the world’s foremost communications, networking, storage system and information technology vendors. At Tundra, we recognize that hiring the best and brightest talent is a big part of what makes us a successful company. We understand that our greatest asset is our employees. Ever dream of designing the future? Design yourself in. Join the Tundra Team! Position Summary As a Physical Implementation Manager you will bring leadership, domain expertise, and new approaches to the organization. You will be responsible for defining and implementing goals and strategies for the Physical Design group while actively promoting the learning and development of others within and outside the group. In addition, you will manage the technical aspects of the Physical Design flows and methods in Tundra. This will include the delivery of new products and the successful integration of new methodologies and tools. Responsibilities In this role you will be responsible for: Manage the development and implementation of new products, technology selection, cell library integration, new flows and methodologies, by engaging external and internal resources to ensure timely completion Lead the effort in establishing CAD and physical design methodologies for 65nm and lower technologies: flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure - Static timing analysis, power and noise analysis and back-end verification across multiple projects Collaborate with other design managers to manage the resource allocation and develop longer-term strategies to ensure future company needs are met Hierarchical physical layout including floor planning, clock tree design, implementation and timing closure Power grid design, implementation and IR drop analysis Physical verification (LVS/DRC) • Generate mask submission documentation
Other possible responsibilities: Participate in the development of die size and cost estimation methodologies Define high speed circuit integrity and clocking methodologies Pad ring analysis and integration System level timing budgets and board/package requirements for signal integrity Interface with ESD, Latch up, I/O and layout specialists to ensure silicon integrity Perform quality assurance procedures on hard macros
RequirementsBachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent Minimum 10 years experience in ASIC development (with a minimum of 3 year in a leadership position) Strong CAD development skills and understanding of Physical Design tools and methods Familiar with Synopsys, Cadence, and Mentor tools Experience with ASIC, SOC and customer owned tools (COT) design flows Possess the ability to work with design, mixed signal design and physical design engineers Positive, can-do attitude and the ability to work well in a team environment Strong collaborative skills with technical and non-technical peers Interested in playing a variety of roles on a team Technical acumen to build and maintain credibility in technical forums and to absorb and apply highly technical information in your work Self-motivated individual who has the ability to collaborate across multiple sites Willing to travel to our design center in India and have flexible working hours to support our multi site R&D organization
If you envision yourself in this role and would like to be part of a team in a dynamic environment, please contact us at 08-027@tundra.com or visit our website at www.tundra.com for more information on our company, products and services. |
