08-025 Principal Engineer, Technology/SERDES Advisor – Ottawa, ON Tundra Semiconductor Corporation, based in Ottawa, Ontario Canada is the global leader in System Interconnect providing world-class customer support, leading-edge semiconductor solutions and design services to the world’s foremost communications, networking, storage system and information technology vendors. At Tundra, we recognize that hiring the best and brightest talent is a big part of what makes us a successful company. We understand that our greatest asset is our employees. Ever dream of designing the future? Design yourself in. Join the Tundra Team! Position Summary As a Principal Engineer, Technology/SERDES Advisor you will be responsible for interfacing with vendors, evaluating and selecting high speed SERDES and Cell library selection. You will work very closely with hardware, packaging and ASIC designers. Responsibilities In this role you will be responsible for: Participate in industry progressions in the technology and SERDES fields Collaborate with technology partners to define, track and ensure current and future product needs are met Collaborate with third party SERDES, design teams to define, track and ensure SERDES meets current and future product needs Drive requirements and selection of SERDES and Cell library for new 65nm designs and smaller geometries Lead development of die size and cost estimation methodologies Lead the selection and integration of third party custom hard macros, such as PLLs and I/Os Define high speed circuit integrity and clocking methodologies Interface with ESD, Latch up, I/O and layout specialists to ensure silicon integrity Performing quality assurance procedures on hard macros Company-wide scope, spanning multiple sites and requiring occasional travel
RequirementsBachelor’s degree in Electrical Engineering, Masters preferred A minimum of 10 years in high speed interface development Successful track record of delivering products to production is a must An understanding of high speed cell designs including SERDES, RAMs, PLL and IO design Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tape-out issues Clear understanding and command over all aspects of physical design including technology, libraries, floor-plan, timing, signal integrity and power dissipation Experience in COT tape-outs, preferably in smaller technologies, to leading foundries (TSMC, UMC, etc) • Self-motivated individual who has the ability to collaborate across multiple sites Willing to travel to our design center in India and have flexible working hours to support our multi site R&D organization
If you envision yourself in this role and would like to be part of a team in a dynamic environment, please contact us at 08-025@tundra.com or visit our website at www.tundra.com for more information on our company, products and services. |
