08-024 Staff Engineer, Static Timing Analysis – Ottawa, ON

Tundra Semiconductor Corporation, based in Ottawa, Ontario Canada is the global leader in System Interconnect providing world-class customer support, leading-edge semiconductor solutions and design services to the world’s foremost communications, networking, storage system and information technology vendors.

At Tundra, we recognize that hiring the best and brightest talent is a big part of what makes us a successful company. We understand that our greatest asset is our employees.

Ever dream of designing the future? Design yourself in. Join the Tundra Team!

Position Summary

As a Staff Engineer in the Design Group you will bring a strong background and demonstrated leadership in defining and driving Static Timing Analysis (STA) methodologies, margin definition, constraint development, physical synthesis, and formal verification in smaller geometries. The proven ability to define and drive these methodologies, and work with a team to create first pass success silicon is a must. Previous experience with Synopsys Pilot flow, layout, and/or front end design is considered a plus.

Responsibilities

In this role you will be responsible for:

• Participate in industry progressions in the fields of STA, synthesis and FV
• Define and drive STA, synthesis and FV methodologies in smaller geometries
• Define clock margins and uncertainties at the block and chip level
• Generate block and chip level timing constraints
• Perform STA at the block and chip level
• Perform block and chip level synthesis
• Perform hierarchical timing closure
• Perform Formal Verification at the block and chip level
• Mentor design team on STA, synthesis and FV

Other possible responsibilities:

• Front-end design
• Hierarchical physical layout to include clock tree design and distribution
• Hierarchical floor planning
• Signal Integrity analysis
• Physical verification

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent
• Minimum 6 years experience in ASIC development
• Ability to take a leadership role in defining STA methodologies, margining, and constraints
• Working knowledge of various physical design tools and platforms, with preference towards Synopsys DC/ICC, Primetime, Formality
• Experience with Synopsys IC design tools, such Astro, JupiterXT, PrimeRail, Hercules, StartRCXT and custom layout tools such as Laker and/or Virtuoso
• Good understanding of DFT modes and DFT timing requirements
• Good documentation and presentation skills
• Positive, can-do attitude and the ability to work well in a team environment
• Knowledge of Verilog or VHDL, Perl, TCL, Unix, MS Windows and MS Office environment and tools
• The ability to collaborate with technical peers across multiple sites, with an interest in playing a variety of roles on a team including leadership. This may require some travel.

If you envision yourself in this role and would like to be part of a team in a dynamic environment, please contact us at 08-024@tundra.com or visit our website at www.tundra.com for more information on our company, products and services.